Article : Design And Implementation Of High Secured Low Complex CRYPTO Devices With High Fault Coverage

Title

Design And Implementation Of High Secured Low Complex CRYPTO Devices With High Fault Coverage

Author

Y. Richard Jayanand, P.Rajeswari

The main motive of this project is to design a crypto device with low complexity and high security by using “ADVANCED AES” Algorithm along with BIST technique. The selective
application of technological and related procedural safeguards is an important responsibility of every Federal organization in providing adequate security to its electronic data systems and coming to BIST concept there are two main functions that must be performed on-chip in order to implement built-in self-test (BIST): test pattern generation and output response analysis. The most common BIST schemes are based on pseudorandom test pattern generation using linear feedback shift registers (LFSR’S) and output response compaction using signature analyzers. To accomplish high security for a system we are using the crypto devices
technique in our project.

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