Article : High-Speed WLAN Using 64-Point FFT Implementation Into Low-Cost FPGA

Title

High-Speed WLAN Using 64-Point FFT Implementation Into Low-Cost FPGA

Author

G.Chitti Hanumantha Rao, A.Pramod Kumar

A novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The processor completes one parallel-to-parallel 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.

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