The main objective of this project is to design a fault diagnoses system for detection of any software or hardware or permanent failures in the embedded read only memories. BIST controller, along with row selector and column selector is designed to meet requirements of at speed test thus enabling detection of timing defects.The proposed approach offers a simple test flow and does not require intensive interactions between a BIST controller and a tester. The scheme rests on partitioning of rows and columns of the memory array by employing low cost test logic. It is designed to meet requirements of at-speed test thus enabling detection of timing defects.
Indian Member 40.00
Others Member 3.00