The main objective of this project is to implement a 32-bit pipelined RISC processor without interlocking stages. MIPS concept follows the same theory using VLIW processor. MIPS measures roughly the number of machine instructions that a computer can execute in one second. Reduced instruction is the main criteria used to develop in this processor. With a single instruction scheme, more executions can be done using S.I.M.E. processor. Architecture based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance level in embedded system. In VLIW architecture, the effectiveness of these processors depends on the ability of compilers to provide sufficient instruction level parallelism (ILP) in program code.
Indian Member 40.00
Others Member 3.00