Article : Low Dense Packed Fused Floating Point FFT With Optimized Complex Structures

Title

Low Dense Packed Fused Floating Point FFT With Optimized Complex Structures

Author

P. Sheela, M. Ramesh Kumar

A new VLSI architecture for real-time pipeline FFT processor is proposed in this project. In this project, both radix-2 and radix-4 floating point butterflies are implemented more efficiently with the two fused floating-point operations. The fused operations are a two-term dot product and add-subtract unit. Both discrete and fused radix processors are implemented; compared in regarded with area wise.

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